1. Field of the Invention
The present invention relates to a structure and a manufacturing method of an insulated gate semiconductor device having an SOI (silicon-on-insulator) structure, particularly an insulated-gate field-effect transistor (hereinafter referred to simply as IG-FET). An example of the insulated-gate semiconductor device having a SOI structure is a semiconductor device formed on an SOS (silicon-on-sapphire) substrate or a SIMOX (separated-by-implanted oxygen) substrate.
In particular, the invention relates to a technique that is effective in forming a very small element having a channel length of less than 0.35 μm (particularly less than 0.1 μm). Thus, the invention can be applied to various semiconductor integrated circuits such as ICs, VLSIs, and ULSIs that are formed by integrating IG-FETs.
The term “semiconductor device” as used in this specification means a “device or apparatus that utilizes a semiconductor to operate for an intended purpose,” and covers not only semiconductor elements such as an IG-FET but also integrated circuits formed by integrating semiconductor elements, and even electronic apparatuses incorporating such integrated circuits. In the specification, for convenience of description, various terms such as a semiconductor element, an integrated circuit, and an electronic apparatus are used where appropriate.
In another aspect, the present invention relates to the configuration of a nonvolatile memory formed by using a semiconductor. In particular, the invention for the nonvolatile memory in which the channel length is 2 μm or less or even 0.5 μm or less.
2. Description of the Related Art
In recent years, integrated circuits such as VLSIs are being miniaturized steadily, and the width of interconnections comes to decrease to 0.35-0.1 μm or less than 0.35 μm, or even to less than 0.01 μm (dimensions of a deep submicron processing range).
On the other hand, low power consumption is also required, which makes the lower power consumption characteristic of CMOS ICs indispensable. Where a CMOS IC is miniaturized, a problem of a latch-up phenomenon may occur between an n-type FET and a p-type FET. IG-FETs having an SOI structure solve this problem.
Because of complete insulation between a substrate and an element, IG-FETs having an SOI structure can greatly reduce a parasitic capacitance occurring there and hence allow pursuit of high-speed operation.
Thus, semiconductor devices having an SOI structure now attract much attention as next-generation high-speed elements and demand for those is expected to increase further in the future.
Such semiconductor elements have been miniaturized according to the scaling rule, and it is generally known that miniaturization of an integrated circuit leads to improvements in its characteristics. However, in microprocessing in a submicron range, problems may occur where the scaling rule does not apply in simple form.
A typical example of such problems is the short channel effects. The short channel effects are caused by a phenomenon that as the width of the gate electrode becomes shorter, that is, the channel forming region becomes shorter, the charge in the channel forming region, which should be controlled by the gate voltage, comes to be also influenced by the depletion layer charge and electric field and the potential profile in the source/drain region.
FIG. 19 shows the above phenomenon in a simplified manner. FIG. 19 shows a conventional semiconductor device formed on a SIMOX substrate in which reference numerals 3301 and 3302 denote a silicon substrate and a buried oxide layer formed by oxygen implantation, respectively. A crystalline semiconductor layer (single crystal silicon layer) is disposed on the buried oxide layer 3302, and a source region 303, a drain region 304, a channel region 3305, and a gate electrode 3306 are formed in or on the crystalline semiconductor layer. A broken line 3307 denotes a depletion layer that is formed when the drain voltage Vd is small.
Normally, the current flowing through the channel region 3305 is controlled only by the gate voltage Vg. In this case, the portion of the depletion layer (indicated by the broken line 3307) in the vicinity of the channel region 3305 is substantially parallel with the channel, to allow formation of a uniform electric field.
However, as the drain voltage Vd is increased, the depletion layer in the vicinity of the drain region 3304 extends toward the channel region 3305 and the source region 3303, so that the charge and the electric field in the drain depletion layer come to influence the depletion layer in the vicinity of the source region 3303 and the channel region 3305 as indicated by a solid line 3308. As a result, the on-current varies depending on a complex electric field profile and is hard to control only by the gate voltage Vg.
Referring to FIG. 20, a description will be made of an energy state in and around the channel forming region in a state that the short channel effects occur. In FIG. 20, solid lines represent an energy band diagram including a source region 3401, a channel forming region 3402, and a drain region 3403 in a state that the drain voltage Vd is 0 V.
When a sufficiently large drain voltage Vd is applied, the energy band diagram changes to one indicated by broken lines in FIG. 20. That is, the depletion layer charge and electric field in the drain region 3403 formed by the drain voltage Vd influence the depletion layer charge in the source region 3401 and the channel forming region 3402, and the energy (potential) profile varies continuously from the source region 3401 to the drain region 3403.
In semiconductor elements, say, IG-FETs, the short-channel effects typically appear as a reduction in threshold voltage Vth and a reduction in device breakdown voltage due to the punch-through phenomenon. It is known that if the degree of influence of the gate voltage on the drain current is lowered by the punch-through phenomenon, the subthreshold characteristic is deteriorated.
The reduction in threshold voltage occurs in both n-channel and p-channel FETs in similar manners. The degree of the threshold voltage reduction depends on not only the drain voltage but also other various parameters such as the substrate impurity concentration, the source/drain diffusion layer depth, the gate oxide film thickness, and the substrate bias voltage.
Although the reduction in threshold voltage is desirable for the purpose of reducing the power consumption, in general a resulting reduction in the drive voltage of an integrated circuit causes demerits such as a difficulty in improving the frequency characteristic.
Further, when the channel length is shortened, the drain-side depletion layer is connected to the source-side depletion layer to lower the diffusion potential in the vicinity of the source, which in turn causes a current flow between the source and the drain even if a channel is not formed there. This is called the punch-through phenomenon.
When the punch-through phenomenon occurs, the drain current is not saturated even in the saturation range. Since a large current comes to flow as the drain voltage is increased, the source-drain breakdown voltage is considerably reduced which is a problem.
The deterioration in subthreshold characteristic due to the punch-through phenomenon means an increase in subthreshold coefficient (S-value), which in turn means deterioration in the switching characteristic of a FET. FIG. 21 shows an influence of the short channel effects appearing in the subthreshold characteristic.
FIG. 21 is a graph in which the horizontal axis represents the gate voltage Vg and the vertical axis represents the drain current Id. The S-value is the reciprocal of the slope (i.e., subthreshold characteristic) in range 2501. FIG. 21 shows how the characteristic varies as the channel length is shortened gradually in the arrowed direction.
It is seen that the slope of the characteristic decreases (the S-value increases) as the channel length is shortened, which means that the switching characteristic of a FET is more deteriorated as the channel length is shortened.
Various techniques have been proposed as means for suppressing the above-described short channel effects. For example, it was reported that in an SOI structure in which a substrate and an element are insulated from each other by a buried oxide film (by using a bonding technique, ion implantation, or some other technique), thinning the buried oxide film is effective in suppressing the short channel effects. However, this technique does not provide a complete solution.
A semiconductor device having an SOI structure in which the channel length is very short, i.e., about 0.1 μm, has a feature that impurity elements exist in the channel region at an extremely low probability (from one to some). Even at the room temperature, a phenomenon was observed that electrons move faster than in the ordinary case (the velocity overshoot effect; see K. Ohuchi et al., Jpn. J. Appl. Phys., Vol. 35, p. 960, 1996).
A high-speed semiconductor device was proposed whose high-speed operation performance was improved by utilizing the above effect. However, in such a high-speed semiconductor device, at present, the problems such as the punch-through phenomenon as one of the short channel effects and the associated deterioration in breakdown voltage (described above) remain unsolved.
As a means for suppressing the reduction in threshold voltage as one of the short channel effects, a technique has been employed in which an impurity element imparting one type of conductivity is added uniformly to the overall channel forming region and the threshold voltage is controlled by its addition amount. However, this method has a problem of a reduction in carrier mobility because the added impurity scatters carriers.
A single crystal silicon substrate as a mother substrate of an SOI substrate is manufactured by a FZ method with a very low oxygen content or a CZ method which allows oxygen to be contained to a certain extent to reduce stress and prevent a warp. Usually, a single crystal silicon substrate by the CZ method is used for memory ICs and logic ICs.
However, in a single crystal silicon substrate manufactured by the CZ method, the amount of warp increases due to a heat history and other factors as the oxygen content is reduced. Conversely, if the oxygen content is increased to such a level (usually, about 1-2×1018 atoms/cm3) that the amount of warp becomes sufficiently small, there may occur a case that oxygen atoms prevent movement of carriers.
In the current semiconductor industry, semiconductor integrated circuits that are integrated to an extreme, and the key point for this purpose is to what extent each semiconductor element can be miniaturized. However, even if a technique for forming a fine pattern in the deep submicron range were developed, the above-described problems of the short channel effects would be fatal obstructions to the miniaturization of semiconductor elements.
The IC memories that perform data storage and holding in computers are generally classified into the RAM and the ROM. Examples of the RAM (random access memory) are the DRAM (dynamic RAM) and the SRAM (static RAM). If the power is turned off, data stored in the DRAM or the SRAM are lost.
On the other hand, examples of the ROM (read-only memory) are the mask ROM and the PROM (programmable ROM). The mask ROM and the PROM have an advantage that even if the power is turned off, data stored there are not lost. The PROM is classified into the EPROM (erasable PROM) in which data erasure is performed by using ultraviolet light, the EEPROM (electrically erasable PROM) in which data erasure is performed electrically, the flash memory (flash EEPROM) in which data erasure is performed en bloc electrically, and other types.
To fully utilize their marked advantage of permanent data holding, studies and developments on nonvolatile memories have been made energetically. At present, the possibility of using nonvolatile memories instead of magnetic memories is being discussed.
As for such IC memories, it is necessary to not only improve the reliability and performance but also increase the storage capacity. That is, as in the case of other types of ICs, such memory ICs are being developed according to the scaling law while miniaturization techniques are always adopted.
However, since basically nonvolatile memories store data according to the same principle of operation as field-effect transistors (hereinafter referred to as FETs), the short channel effect, which is known as causing serious problems in the FET operation, also causes serious problems in the operation of nonvolatile memories as the miniaturization advances.
In particular, the phenomenon called “punch-through” decreases the source-drain breakdown voltage and hence makes the current control with the gate electrode difficult. A SSW-DSA structure (Nikkei Microdevices, pp. 47-48, May issue, 1992) is a conventional example of increasing the punch-through resistance.
In the field of the FET, the SSW-DSA structure is a structure that utilizes a technique called a pocket structure in which an impurity region having the same conductivity type as the substrate is provided in the channel-drain junction portion. This structure can prevent the occurrence of a punch-through phenomenon by suppressing the expansion of the drain depletion layer.
However, in nonvolatile memories, electron-hole pairs are generated by positively causing impact ionization in the channel-drain junction portion. Therefore, a large amount of holes flow to the substrate side as electrons are injected into the floating gate.
However, in the SSW-DSA structure, a large amount of holes thus generated act in no other way than flow into the substrate terminal. This may cause a problem that a parasitic source-substrate-drain bipolar is formed to cause a kink phenomenon (an abnormal increase in drain current).